The present invention generally relates to driver circuits for driving analog devices, and in particular to a high power digital output circuit for producing high power digital signals that drive an analog device such as audio-speaker via a suitable filtering circuit.
The use of digital power amplifiers is spreading for example in the audio amplifiers because of the high quality sound obtained from such digital systems. By using the digital power amplifiers, one can eliminate the analog signal processing from the entire audio system except for the final stage for driving the audio speakers. Thereby, an ideal reproduction or processing of the audio signals is achieved without being hampered by the distortion or noise pertinent to the analog audio systems. Such a digital power amplifier is particularly suited for reproducing the audio signals from the digital signal source such as the digital audio disc players or digital tape recorders that produce the output audio signals in the form of digital data.
FIG. 1 shows an example of such a digital audio system.
Referring to FIG. 1, a digital signal source 1 supplies a digital output signal to a demodulator 3 via an optical fiber cable 2. The demodulator 3 reproduces, in response, a pulse code modulation (PCM) signal that is supplied to a converter 4 for conversion to a pulse width modulation (PWM) signal. The converter 4 produces the foregoing PWM signal and a logic inversion thereof simultaneously in correspondence to the PCM signal supplied thereto, and supplies the same to a digital driver circuit 5 that is the subject matter of the present invention. The digital driver circuit 5, in turn, drives output circuits 6a and 6b each comprising a pair of high power MOS transistors connected in series between a voltage source V.sub.CC and the ground V.sub.EE. The output circuits 6a and 6b are driven complementary such that when the circuit 6a produces an output current with a voltage of V.sub.CC, the output circuit 6b produces a ground level voltage V.sub.EE, and such that when the circuit 6b produces an output current with the voltage of V.sub.CC, the output circuit 6a produces the ground level voltage.
The output circuits 6a and 6b drive a speaker 8 via respective low pass filters 7a and 7b that smooths the pulse width modulation signals supplied thereto from the output circuits 6a and 6b. Thereby, a high power amplitude modulation signal of which amplitude changes about a level of V.sub.CC /2 is obtained at the speaker 8.
FIG. 2 shows the construction of the conventional driver circuit 5 including the MOS output circuits 6a and 6b.
Referring to FIG. 2, there are provided drive circuits 1a and 1b respectively connected to input terminals T.sub.i1 and T.sub.i2 to which a PWM signal D and its logic inversion D are supplied. The drive circuit 1a has an output terminal connected to a base of a bipolar transistor T.sub.r3, while the drive circuit 1b has an output terminal connected to a base of another bipolar transistor T.sub.r4. The transistors Tr.sub.3 and Tr.sub.4 are connected in series between the voltage source V.sub.CC and the ground level V.sub.EE such that the transistor Tr.sub.3 has a collector connected to the voltage source V.sub.CC and an emitter connected to a collector of the transistor Tr.sub.4. The transistor Tr.sub.4, on the other hand, has an emitter connected to the ground V.sub.EE. Similarly, there are provided drive circuits 1c and 1d respectively connected to input terminals T.sub.i3 and T.sub.i4 to which the inverted PWM signal D and the non-inverted PWM signal D are supplied respectively, wherein the drive circuit 1c has an output terminal connected to a base of a bipolar transistor Tr.sub.5, the drive circuit 1d has an output terminal connected to a base of another bipolar transistor Tr.sub.6. The transistors Tr.sub.5 and Tr.sub.6 are connected in series between the voltage source V.sub.CC and a ground level V.sub.EE such that the transistor Tr.sub.5 has a collector connected to the voltage source V.sub.CC and an emitter connected to a collector of the transistor Tr.sub.6. On the other hand, the transistor Tr.sub.6 has an emitter connected to the ground V.sub.EE.
The output circuit 6a or 6b includes power MOS transistors Tr.sub.1 and Tr.sub.2 connected in series between the voltage source V.sub.CC and V.sub.EE such that the MOS transistor Tr.sub.1 has a drain connected to the voltage source V.sub.CC, a source connected to the drain of the MOS transistor Tr.sub.2, while the MOS transistor Tr.sub.2 has a source connected to the ground V.sub.EE. Further, the transistor Tr.sub.1 has a gate connected to a node n.sub.1 where the emitter of the bipolar transistor Tr.sub.3 and the collector of the bipolar transistor Tr.sub.4 are connected with each other, the transistor Tr.sub.2 has a gate connected to another node n.sub.2 where the emitter of the transistor Tr.sub.5 and the collector of the transistor Tr.sub.6 are connected with each other. The output of the circuit 6a or 6b is obtained from an output terminal T.sub.0 that is connected to a node n.sub.3 where the source of the transistor Tr.sub.1 is connected to the drain of the transistor Tr.sub.2.
In this conventional driver circuit 5, the transistors Tr.sub.3 and Tr.sub.4 are turned on and turned off in the complementary manner in response to the complementary input signals D and D such that when the transistor Tr.sub.3 is turned on, the transistor Tr.sub.4 is turned off and vice versa. Similarly, the transistors Tr.sub.5 and Tr.sub.6 are turned on and turned off complementary in response to the complementary input signals D and D such that when the transistor Tr.sub.5 is turned on, the transistor Tr.sub.6 is turned off and vice versa. Thus, when the transistor Tr.sub.3 is turned on in response to the high level signal at the input terminal T.sub.i1, the transistor Tr.sub.4 is turned off in response to the low level signal at the input terminal T.sub.i2. Thereby, a high level signal appears at the node n.sub.1 and the MOS transistor Tr.sub.1 is turned on in response thereto. At the same time to the high level signal at the input terminal T.sub.i1, there appear a low level signal at the input terminal T.sub.i3 and a high level signal at the input terminal T.sub.i4, and the transistor Tr.sub.5 is turned off while the transistor Tr.sub.6 is turned on. Thereby, a low level signal appears at the node n.sub.2, and the transistor Tr.sub.2 is turned off in response thereto. Thus, a large output current is obtained at the output terminal T.sub.0 When the logic state of the signals at the input terminals T.sub.i1 -T.sub.i4 is inverted, on the other hand, the transistor Tr.sub.3 is turned off, the transistor Tr.sub.4 is turned on, the transistor Tr.sub.5 is turned on, and the transistor Tr.sub.6 is turned off. As a result, the transistor Tr.sub.1 is turned off and the transistor Tr.sub.2 is turned on. Thereby, the output terminal T.sub.0 is grounded and no output current obtained therefrom. By smoothing the PWM output current at the output terminal T.sub.0 by the filtering circuits, one obtains the desired output current.
In this conventional driver circuit 5, there exists a problem in that, when the gate voltage of the transistors Tr.sub.1 and Tr.sub.2 is inverted, there may appear a situation where both of the transistors Tr.sub.1 and Tr.sub.2 are turned on momentarily, depending on the characteristic of the transistors Tr.sub.1 and Tr.sub.2. When this occurs, a feed-through current flows from the voltage source V.sub.CC to the ground, and such a feed-through current causes a distortion in the reproduced audio signal and increases the power consumption of the amplifier. The distortion in the reproduced audio signal of course deteriorates the quality of the reproduced sound while the problem of increased power consumption causes a serious problem in the battery driven systems such as a portable audio system.